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general description the MAX3890 serializer is ideal for converting 16-bit- wide, 155mbps parallel data to 2.5gbps serial data in atm and sdh/sonet applications. operating from a single +3.3v supply, this device accepts low-voltage differential-signal (lvds) clock and data inputs for interfacing with high-speed digital circuitry, and deliv- ers positive-referenced emitter-coupled logic (pecl) serial data and clock outputs. a fully integrated phase- locked loop (pll) synthesizes an internal 2.5ghz serial clock from a 155.52mhz, 77.76mhz, 51.84mhz, or 38.88mhz reference clock. a loopback data output is provided to facilitate system diagnostic testing. the MAX3890 is available in the extended temperature range (-40? to +85?) in a 64-pin tqfp exposed-pad (ep) package. applications 2.5gbps sdh/sonet transmission systems 2.5gbps atm/sonet access nodes add/drop multiplexers digital cross-connects atm backplanes features single +3.3v supply 495mw power consumption exceeds ansi, itu, and bellcore specifications 155mbps (16-bit wide) parallel to 2.5gbps serial conversion clock synthesis for 2.5gbps multiple clock reference frequencies (155.52mhz, 77.76mhz, 51.84mhz, 38.88mhz) lvds parallel clock and data inputs additional high-speed output for system loopback testing MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs ________________________________________________________________ maxim integrated products 1 MAX3890 max3867 slbo- gnd 155mhz ref clock input pdi0+ rclk+ rclk- v cc clkset slbo+ fil- fil+ +3.3v overhead generation pclko- pclko+ pclki- pclki+ pdi15- pdi15+ pdi0- this symbol represents a transmission line of characteristic impedance (z 0 = 50 ? ). sos 330nf ttl optional connection to max3880 for system loopback testing. +3.3v +3.3v +3.3v v cc sdo+ sdo- sclko- sclko+ 130 ? 130 ? 130 ? 130 ? 82 ? 82 ? 82 ? 82 ? typical operating circuit 19-1498; rev 1; 12/99 part MAX3890ecb -40? to +85? temp. range pin-package 64 tqfp-ep* ordering information pin configuration appears at end of data sheet. evaluation kit available * ep = exposed pad for free samples and the latest literature, visit www.maxim-ic.com or phone 1-800-998-8800. for small orders, phone 1-800-835-8769.
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, differential lvds loads = 100 ? ?%, pecl loads = 50 ? ?% to (v cc - 2v), cml loads = 50 ? ?% to v cc , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. terminal voltage (with respect to gnd) v cc .......................................................................-0.5v to +5v all inputs, fil+, fil- ...............................-0.5v to (v cc + 0.5v) output current lvds outputs (pclko?................................................10ma pecl outputs (sdo? sclko?....................................50ma cml outputs (slbo?....................................................15ma continuous power dissipation (t a = +85?) tqfp-ep (derate 44.8mw/? above +85?) ......................1w operating temperature range ...........................-40? to +85? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? t a = 0? to +85? pecl outputs unterminated, sos = low t a = 0? to +85? differential input voltage = 100mv conditions v v cc - 1.025 v cc - 0.88 v oh output voltage high ma 150 230 i cc supply current v 0.925 v ol output voltage low v 1.475 v oh output voltage high ? 85 100 115 r in differential input resistance mv 60 v hyst threshold hysteresis v v cc - 1.81 v cc - 1.62 v ol output voltage low v 0 2.4 v i input voltage range mv -100 100 v idth differential input threshold units min typ max symbol parameter figure 5 % ?.5 ?0 ? r o change in magnitude of single-ended output resistance for complementary outputs ? 40 95 140 r o single-ended output resistance mv ?5 ? v os change in magnitude of output offset voltage for complementary states mv 250 400 | v od | differential output voltage mv ?5 ?| v od | change in magnitude of differential output voltage for complementary states v 1.125 1.275 v os output offset voltage t a = -40? v cc - 1.085 v cc - 0.88 t a = -40? v cc -1.83 v cc - 1.555 pecl outputs (sdo? sclko? lvds inputs and outputs (pclko? pdi_? pclki? rclki?
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs _______________________________________________________________________________________ 3 note 1: ac characteristics guaranteed by design and characterization. note 2: setup and hold times are relative to the rising edge of pclki+, measured by applying a 155.52mhz differential parallel clock with rise/fall time = 1ns (20% to 80%). see figure 2. note 3: for f rclk = 38.88mhz, the minimum reference clock amplitude is 200mv. (note 2) (note 2) figure 2 jitter bandwidth = 12khz to 20mhz, rclk amplitude > | v idth | (note 3) 20% to 80% conditions ps 700 t h parallel data-hold time ps 300 t su ghz 2.488 f sclk serial clock rate parallel data setup time ns 0 +4.0 t skew pclko to pclki skew ps rms 3 0 output jitter generation (sclko? ps 120 t r, t f pecl differential output rise/fall time units min typ max symbol parameter ac electrical characteristics (v cc = +3.0v to +3.6v, differential lvds load = 100 ? ?%, pecl loads = 50 ? ?% to (v cc - 2v), cml loads = 50 ? ?% to v cc , t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) (note 1) mhz 155.52 f pclki parallel input clock rate 20% to 80%, f = 155.52mhz ns 1.0 t r , t f reference clock input (rclki) rise/fall time 20% to 80% ns 1.0 t r , t f parallel clock output (pclko) rise/fall time sclko rising edge to sdo edge ps 110 290 t sclk-sd serial clock output (sclko) to serial-data output (sdo) delay dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, differential lvds loads = 100 ? ?%, pecl loads = 50 ? ?% to (v cc - 2v), cml loads = 50 ? ?% to v cc, t a = -40? to +85?, unless otherwise noted. typical values are at v cc = +3.3v, t a = +25?.) conditions ? -10 10 i il v 0.8 v il input voltage low ? -10 10 i ih input current high input current low units min typ max symbol parameter ? 50 r o single-ended output resistance mv 100 400 | v od | differential output voltage clkset = 0 or v cc ? ?00 i clkset clkset input current v 2.0 v ih input voltage high ttl input (sos) programming input (clkset) current mode logic (cml) outputs (slbo?
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs 4 _______________________________________________________________________________________ 200 100 -50 -25 25 100 supply current vs. temperature 120 160 180 MAX3890-01 temperature (?) supply current (ma) 050 140 75 pecl outputs unterminated 5ps/div serial-data output jitter MAX3890-03 total wideband rms jitter = 2.155ps peak-to-peak jitter = 15.7ps f rck = 155.52mhz f rck = 155.52mhz 50ps/div serial-data output eye diagram MAX3890-02 0 0.5 1.0 2.0 1.5 2.5 3.0 100 150 200 250 300 350 400 output jitter generation vs. rclk amplitude MAX3890 toc04 rclk amplitude (mv) output jitter generation (ps) f rclk = 51.84mhz f rclk = 38.88mhz f rclk = 155.52mhz f rclk = 77.76mhz typical operating characteristics (v cc = +3.3v, pecl loads = 50 ? ?%, t a = +25?, unless otherwise noted.)
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs _______________________________________________________________________________________ 5 pin description name function 1, 17, 33, 48, 49, 63 gnd ground 2, 5, 7, 10, 13, 14, 32, 56, 60, 64 v cc +3.3v supply voltage pin 3 slbo- system loopback inverting output. enabled when sos is high. 4 slbo+ system loopback noninverting output. enabled when sos is high. 12 sdo+ noninverting pecl serial-data output 9 sclko+ noninverting pecl serial clock output 6 sos system loopback output select. system loopback disabled when low. 55 pclko- inverting lvds parallel clock output. use positive transition of pclko to clock the over- head management circuit. 54 pclko+ noninverting lvds parallel clock output. use positive transition of pclko to clock the overhead management circuit. 57 rclk+ noninverting lvds reference clock input. connect an lvds-compatible crystal refer- ence clock to the rclk inputs. 59 clkset reference clock rate programming pin: clkset = v cc : reference clock rate = 155.52mhz clkset = open: reference clock rate = 77.76mhz clkset = 20k ? to gnd: reference clock rate = 51.84mhz clkset = gnd: reference clock rate = 38.88mhz 58 rclk- inverting lvds reference clock input. connect an lvds-compatible crystal reference clock to the rclk inputs. 61 fil- filter capacitor input. connect a 330nf capacitor between fil+ and fil-. 18, 20, 22, 24, 26, 28, 30, 34, 36, 38, 40, 42, 44, 46, 50, 52 pdi15+ to pdi0+ noninverting lvds parallel data inputs. data is clocked on the pclki positive transition. 62 fil+ filter capacitor input. connect a 330nf capacitor between fil+ and fil-. 8 sclko- inverting pecl serial clock output 11 sdo- inverting pecl serial-data output 15 pclki+ noninverting lvds parallel clock input. connect the incoming parallel-clock signal to the pclki inputs. note that data is updated on the positive transition of the pclki signal. 16 pclki- inverting lvds parallel clock input. connect the incoming parallel-clock signal to the pclki inputs. note that data is updated on the positive transition of the pclki signal. 19, 21, 23, 25, 27, 29, 31, 35, 37, 39, 41, 43, 45, 47, 51, 53 pdi15- to pdi0- inverting lvds parallel data inputs. data is clocked on the pclki positive transition. ep exposed pad ground. this must be soldered to a circuit board for proper thermal performance (see package information ).
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs 6 _______________________________________________________________________________________ detailed description the MAX3890 converts 16-bit-wide, 155mbps data to 2.5gbps serial data (figure 1). it is composed of a 16- bit parallel input register, a 16-bit shift register, control and timing logic, pecl output buffers, lvds input/out- put buffers, and a frequency-synthesizing pll (consist- ing of a phase/frequency detector, loop filter/amplifier, voltage-controlled oscillator (vco), and prescaler). the pll synthesizes an internal 2.5gbps reference used to clock the output shift register. this clock is generated by locking onto the external 155.52mhz, 77.76mhz, 51.84mhz, or 38.88mhz reference-clock signal (rclk). the incoming parallel data is clocked into the MAX3890 on the rising transition of the parallel-clock- input signal (pclki). proper operation is ensured if the parallel input register is latched within a window of time (t skew ) that is defined with respect to the parallel- clock-output signal (pclko). pclko is the synthe- sized 2.5gbps internal serial-clock signal divided by 16. the allowable pclko-to-pclki skew is 0 to +4ns. this defines a timing window after the pclko rising edge, during which a pclki rising edge may occur (figure 2). system loopback the MAX3890 is designed to allow system loopback test- ing. the loopback outputs (slbo+, slbo-) of the MAX3890 may be directly connected to the loopback inputs of a deserializer (such as the max3880) for system diagnostics. to enable the slbo outputs, apply a ttl logic-high signal to the sos input. note: the same signal that controls the sos enable input may also be used to control the sis enable input on the max3880. MAX3890 pdi15+ pdi15- 16-bit parallel input register phase/freq detect divide by 16 16-bit shift register lvds lvds pclki- pclki+ rclki- rclki+ fil+ fil- clkset pclko+ pclko- vco pecl sdo+ sdo- shift latch lvds pdi1+ pdi1- lvds pdi0+ pdi0- lvds lvds prescaler filter pecl sclko+ sclko- cml slbo+ slbo- sos pll figure 1. functional diagram
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs _______________________________________________________________________________________ 7 low-voltage differential-signal inputs and outputs the MAX3890 has lvds inputs and outputs for inter- facing with high-speed digital circuitry. the lvds standard is based on the ieee 1596.3 lvds specifi- cation. this technology uses 250mv to 400mv differ- ential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immu- nity. for proper operation, the parallel clock lvds outputs (pclko+, pclko-) require 100 ? differential dc termi- nation between the inverting and noninverting outputs. do not terminate these outputs to ground. the parallel data and parallel clock lvds inputs (pdi_+, pdi_-, pclki+, pclki-, rclk+, rclk-) are internally terminated with 100 ? differential input resis- tance, and therefore do not require external termina- tion. pecl outputs the serial-data pecl outputs (sdo+, sdo-, sclko+, sclko-) require 50 ? dc termination to (v cc - 2v) (see the alternative pecl-output termination section). current-mode logic outputs the system loopback outputs (slbo+, slbo-) of the MAX3890 are designed using cml. the configuration of the MAX3890 current-mode logic (cml) output cir- cuit includes internal 50 ? back termination to v cc (figure 3). these outputs are intended to drive a 50 ? transmission line terminated with a matched load impedance. t skew serial output data (sdo) note: signals shown are differential. for example, pclko = (pclko+) - (pclko-). *pdi 15 = d15; pdi14 = d14; ...pdi0 = d0. this figure is not intended to show a specific timing relationship between parallel input data and serial output data. parallel input data (pdi_) valid parallel data* pclki pclko t su t h d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d10 d11 d12 d13 d14 *d15 figure 2. timing diagram
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs 8 _______________________________________________________________________________________ MAX3890 sclko+ or sdo+ sclko- or sdo- v cc - 2v 50 ? 50 ? z 0 = 50 ? high- impedance inputs z 0 = 50 ? MAX3890 sclko+ or sdo+ sclko- or sdo- +3.3v 130 ? 130 ? 82 ? 82 ? z 0 = 50 ? pecl inputs z 0 = 50 ? figure 4. alternative pecl-output termination applications information alternative pecl-output termination figure 4 shows alternative pecl-output termination methods. use thevenin-equivalent termination when a (v cc - 2v) termination voltage is not available. if ac- coupling is necessary, be sure that the coupling capac- itor is placed following the 50 ? or thevenin-equivalent dc termination. layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies and keep ground connections short. use multiple vias where possible. also, use controlled-impedance transmission lines to interface with the MAX3890 clock and data inputs and outputs. exposed pad (ep) package the ep 64-pin tqfp incorporates features that provide a very low thermal resistance path for heat removal from the ic to a pc board. the MAX3890? exposed pad must be soldered directly to a ground plane with good thermal conductance. figure 3. current-mode logic 50 ? 50 ? v cc slbi+ slbi- v cc 50 ? 50 ? slbo+ slbo- gnd esd structure input circuit output circuit
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs _______________________________________________________________________________________ 9 figure 5. driver output levels single-ended output | v od | v pd- v oh v os v odp-p = v pd+ - v pd- -v od +v od 0v 0v (diff) v ol v pd+ differential output v pd+ - v pd- d pd+ r l = 100 ? v od pd- v
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs 10 ______________________________________________________________________________________ chip information transistor count: 4126 sdo- fil+ pdi15+ tqfp-ep top view pdi15- pdi14+ pdi14- pdi13+ pdi13- pdi12+ pdi12- pdi11+ pdi11- pdi10+ pdi10- pdi9+ pdi9- v cc gnd v cc fil- rclk- clkset v cc rclk+ pclko+ pclko- pdi0+ pdi0- pdi1+ pdi1- gnd pdi2- pdi2+ pdi3- pdi3+ pdi4- pdi4+ pdi5- pdi5+ pdi6- pdi6+ pdi7- pdi7+ pdi8- pdi8+ gnd v cc sclko+ sclko- v cc sos pclki- pclki+ v cc v cc sdo+ v cc slbo+ slbo- v cc gnd gnd gnd v cc 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 52 53 49 50 51 33 34 35 36 37 48 64 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 MAX3890 pin configuration
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs ______________________________________________________________________________________ 11 package information 64l, tqfp.eps
MAX3890 +3.3v, 2.5gbps, sdh/sonet 16:1 serializer with clock synthesis and lvds inputs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 1999 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued)

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